(1) Field of the Invention
The present invention relates generally to a structure and manufacturing process of a semiconductor device which provides improved ESD protection for internal active semiconductor devices and more particularly to a semiconductor SCR like device which when used with shallow trench isolation, provides improved parasitic bipolar characteristics resulting in improved ESD protection performance.
(2) Description of Prior Art
The discharge of electrostatic energy from the human body or other sources known as Electrostatic discharge (ESD) into the input or output pads of integrated circuit semiconductor devices has shown to cause catastrophic failures in these same circuits. This is becoming more important as modern metal oxide semiconductor circuit technology (MOS) is sealed down in size and increased in device and circuit density. Prevention of damage from ESD events is provided by protection devices or circuits on the input or output pads of the active logic circuits which shunt the ESD energy to a second voltage source, typically ground, thereby bypassing the active circuits protecting them from damage. Various devices such as silicon controlled rectifiers (SCR) have been utilized to essentially shunt the high ESD energy and therefore the ESD stress away from the active circuits.
Isolation is required between these ESD protection devices and the active circuit devices, as well as between the active devices themselves. Originally areas of local thick oxide, often called LOCOS or field oxide, have been used to provide this isolation. While having good isolation properties, this isolation method uses more surface area, or “real estate”, than an alternative isolation method using shallow, relatively narrow trenches filled with a dielectric, typically silicon oxide (SIO2), called shallow trench isolation (STI).
While providing good isolation properties, the STI structure has limiting effects on the current triggering and capacity of the SCR ESD protection devices. As discussed in the paper “Semiconductor Process and Structural Optimization of Shallow Trench Isolation-Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks” by Voldman et al., EOS/ESD Symposium 98-151, pages 151 to 160, during STI formation, the STI region is exposed to the etching process, leading to non-planer STI edges where the silicon region extends above the isolation edge. The non-planer STI edge is called “STI pull-down”. The impact of STI pull-down, and the interaction with the salicide process typically used in current contact technology, as well as junction depth reduction of the diode elements bounded by the STI devices, all degrade ESD protection capabilities by reducing the parasitic bipolar current gain, beta, (β). This increases the holding voltage and trigger current of the lateral SCR, reduces lateral heat transfer capability, and possibly limits the type of ESD networks implemented. Among other things, this can result in device failure before the SCR is fully on, or a high on-resistance for the SCR reducing the ESD failure threshold.
FIG. 1A is a simplified cross section of a typical prior art SCR ESD protection device. Shown is a P substrate 10, with an N-well 12 and which contains contact regions N+ 16 and P+ 18. The N-well 12 contact regions are isolated and bounded by the shallow trench isolation (STI) structures 14A, 14B and 14C. The N-well 12 is also bounded by STI elements 14A and 14C. The P substrate also contains N+ contact 20 bounded by STI elements 14C and 14D, and P+ contact 22 bounded by STI structures 14D and 14E. Also depicted in FIG. 1A are parasitic vertical PNP bipolar transistor T1 and lateral NPN bipolar transistor T2 with parasitic resistors R1 and R2. As is well recognized, an SCR device is essentially a P-N-P-N structure as depicted in FIG. 1B. The P+ contact 18 is the anode end of the device and is connected to the active circuit input or output pad 8 as well as to the N+ N-well contact 16. The junction between the P+ contact region 18 and the N-well 12 is the first junction of the SCR.
The N-well 12 and the P substrate 10 form the second junction. The third device junction is formed by the substrate 10 and substrate N+ contact 20, which also is the cathode terminal of the device. N+ contact 20 is connected to a second voltage source 24, typically ground, and also to substrate P+ contact 22. FIG. 1C represents the electrical schematic of the prior art device showing the parasitic vertical bipolar PNP transistor T1 and parasitic lateral NPN bipolar transistor T2 as well as the resistors R1 and R2. A positive ESD voltage event will cause the T1 base-collector junction to go into avalanche conduction, turning on T2 and providing the regenerative conduction action shunting the ESD current to the second voltage source, typically ground. A negative ESD voltage pulse will forward bias the base-collector junction of T1, again shunting the current to the second voltage source.
However, as indicated above, the STI isolation structures inhibit lateral current conduction near the surface, lower the parasitic bipolar semiconductor current gain, and can interfere with device thermal characteristics.
FIG. 2A represents another prior art protection device, a low voltage trigger SCR (LVTSCR). There is no STI between the N-well N+ contact 16 and SCR P+ anode 18. The STI structure has essentially been replaced by a N+ region 28 straddling the N-well to P substrate lateral boundary. A FET gate has been inserted between the N+ region 28 and the N+ region 20 which essentially become the drain and source of a NFET respectively. The NFET source region also functions as the SCR cathode. The prior art LVTSCR device operational trigger voltage is reduced by the NFET device breakdown voltage. The STI elements still reduce the desirable ESD protection characteristics as previously discussed.
FIG. 2B represents a prior art modified lateral SCR. This device does not have the NFET of the LVTSCR, but retains the N+ region 28 straddling the N-well 12 and the P substrate 10 lateral boundary and which provides an additional source of current for triggering the SCR thereby enabling a lower trigger voltage than a more conventional SCR.
The invention in various embodiments allows selective use of STI elements while improving ESD protection by the strategic use of polysilicon gates
The following patents describe ESD protection devices.
U.S. Pat. No. 5,465,189 (Polgreen et al.) shows a SCR with isolation.
U.S. Pat. No. 5,012,317 (Rountree) shows a conventional SCR protection device.
U.S. Pat. No. 4,939,616 (Rountree) sows another SCR type device.
U.S. Pat. No. 6,081,002 (Amerasekera et al.), U.S. Pat. No. 5,629,544 (Voldman et al.), U.S. Pat. No. 6,074,899 (Voldman et al.), U.S. Pat. No. 5,945,713 (Voldman), and U.S. Pat. No. 5,923,067 (Voldman) show related SCR protection devices which use STI elements.
The following technical report discusses STI bound ESD protection networks
“Semiconductor Process and Structural Optimization of Shallow Trench Isolation-Defined and Polysilicon-Bound Source/Drain Diodes for ESD Networks” by Voldman et al., EOS/ESD Symposium 98-151, pages 151 to 160.